Leading Zero Detector
Floating point normalization and instruction decoding rely on finding the most significant set bit in a word. The leading zero detector computes how many positional shifts are required to align a mantissa in arithmetic logic units.
The circuit accepts an 8-bit input D and outputs a 3-bit value Z representing the count of consecutive zeros starting from the most significant bit, D[7]. If all bits in D are zero, Z must output 7.
| D[7:0] | Z | |----------|-----| | 1xxxxxxx | 0 | | 01xxxxxx | 1 | | 001xxxxx | 2 | | 0001xxxx | 3 | | 00001xxx | 4 | | 000001xx | 5 | | 0000001x | 6 | | 00000001 | 7 | | 00000000 | 7 |
Constraints
- Combinational logic only.
- Do not use sequential elements or clocks.
Topics
Solve this problem
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