Clock Enable Inference

High-performance digital systems rely on dedicated clock enable pins to control register updates efficiently. When an engineer writes sequential logic that holds its previous state, synthesis tools must decide whether to route the data through a large feedback multiplexer or to utilize the dedicated clock enable (DFFE) hardware primitive found in modern FPGAs and ASICs. Proper coding style ensures the synthesis tool infers the smaller, faster DFFE primitive rather than wasting area and increasing critical path delay with unnecessary multiplexers.

The module acts as an 8-bit register that captures the data input on the rising edge of the clock only when the enable signal is asserted. When the enable signal is de-asserted, the register ignores the data input and holds its current stored value indefinitely.

The circuit operates on the positive edge of clk. It features an asynchronous, active-low reset rst_n. When rst_n is asserted (driven to 0), the output q is immediately forced to 0 regardless of the clock or enable signals. The reset signal has the highest priority; if rst_n is asserted simultaneously with a clock edge and an active en, the module will still reset. The output q is fully registered.

Cycle 1: rst_n=0, en=0, d=0 → q=0 (Reset overrides all) Cycle 2: rst_n=1, en=1, d=170 → q=170 (Enable asserted, data captured) Cycle 3: rst_n=1, en=0, d=85 → q=170 (Enable de-asserted, state held) Cycle 4: rst_n=1, en=0, d=15 → q=170 (Enable de-asserted, state held) Cycle 5: rst_n=1, en=1, d=200 → q=200 (Enable asserted, new data captured) Cycle 6: rst_n=1, en=0, d=99 → q=200 (Enable de-asserted, state held)

{ "signal": [
  { "name": "clk",   "wave": "p......" },
  { "name": "rst_n", "wave": "01....." },
  { "name": "en",    "wave": "010.10." },
  { "name": "d",     "wave": "======.", "data": ["0", "170", "85", "15", "200", "99"] },
  {},
  { "name": "q",     "wave": "=.====.", "data": ["0", "170", "170", "170", "200", "200"] }
], "head": { "text": "Register captures data when en=1 and holds when en=0." } }

| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; q goes to 0 when asserted | | en | input | 1 | Clock enable; q captures d on posedge clk when 1 | | d | input | 8 | Data input | | q | output | 8 | Registered data output; resets to 8'h00 |

Constraints

• The design must trigger on the positive edge of clk.
• The reset rst_n must be asynchronous and active-low.
• On reset, the output q must be strictly 8'h00.
• The reset signal rst_n has absolute priority over the enable signal en.
• When en is 0, q must retain its previous value without modification.
• The output q must be a registered output, not combinational logic.

Topics

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