Clock Gating Cell with Test Enable

Automatic Test Pattern Generation (ATPG) requires full control over all clocks in a design to achieve high manufacturing fault coverage. A standard clock gate blocks the clock when its functional enable is low, which prevents the ATPG tool from toggling downstream flip-flops. To solve this, clock gating cells include a test override pin that forces the clock on during manufacturing tests.

The module receives a functional enable and a test enable. These two signals must be logically ORed together to create a combined enable. To prevent glitches on the output clock, this combined enable passes through a negative-level sensitive latch. The output of the latch is then ANDed with the input clock to produce the gated output clock.

• Clock edge: The latch is transparent when clk is low and holds its value when clk is high. The AND gate operates continuously.
• Reset type: There is no reset. The latch initializes when clk is low.
• Priority rules: The test enable and functional enable have equal priority through the OR gate.
• Output distinction: The output gclk is the combinational result of the input clk and the registered latch state.

Step 1: clk=0, en=0, te=0 → Latch is transparent; combined enable is 0. gclk=0. Step 2: clk=1, en=0, te=0 → Latch holds 0. gclk=0. Step 3: clk=1, en=1, te=0 → Latch holds 0; ignores the en change while clock is high. gclk=0. Step 4: clk=0, en=1, te=0 → Latch is transparent; combined enable becomes 1. gclk=0 because clk is low. Step 5: clk=1, en=1, te=0 → Latch holds 1. gclk=1. Step 6: clk=1, en=0, te=0 → Latch holds 1; glitch prevented on falling enable. gclk=1.

{ "signal": [
  { "name": "clk",  "wave": "01.01.0." },
  { "name": "en",   "wave": "0.1..0.." },
  { "name": "te",   "wave": "0......." },
  { "name": "gclk", "wave": "0..1.0.." }
], "head": { "text": "Latch blocks enable changes while clk is high to prevent glitches." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Source clock input | | en | input | 1 | Functional enable signal | | te | input | 1 | Test enable; forces clock on when asserted | | gclk | output | 1 | Gated clock output |

Constraints

• The module must use a latch sensitive to clk being low.
• Do not use an edge-triggered flip-flop.
• The OR operation between en and te must happen before the latch.
• All inputs and outputs are exactly 1-bit wide.

Topics

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