Composite ALU Datapath
Central processing units rely on the Arithmetic Logic Unit to execute the core instruction set. This datapath combines addition, subtraction, bitwise logic, and shifting into a single functional block controlled by an instruction decode signal.
The circuit receives two 4-bit data inputs, A and B, and a 3-bit operation code Op. It must produce a 4-bit output Y corresponding to the selected operation.
| Op | Y Output | |------|------------| | 000 | A + B | | 001 | A - B | | 010 | A & B | | 011 | A | B | | 100 | A ^ B | | 101 | ~A | | 110 | A << 1 | | 111 | A >> 1 |
Constraints
- Combinational logic only.
- Implement addition and subtraction using a single shared adder block.
- Route all intermediate results through a multiplexer tree controlled by
Op. - Treat all arithmetic as 4-bit unsigned with wrap-around.
- Shift operations are logical shifts: zero-fill the vacated bits.
Topics
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