Constant Folding Verification
Modern synthesis tools automatically optimize away redundant operations to save area and power. The provided RTL module takes a 4-bit input A and computes the 8-bit output Y using the expression Y = (A * 8) + 0. The synthesizer processes this RTL and generates a gate-level netlist. Inspect the generated netlist to determine the physical hardware instantiated by the tool. Verify the presence or absence of arithmetic cells and trace the wire connections from A to Y.
Constraints
- Input
Ais a 4-bit unsigned integer. - Output
Yis an 8-bit unsigned integer. - Synthesis is targeted for a generic standard cell library without dedicated DSP blocks.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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