Debug a Full Adder Where Sum and Carry Outputs Are Swapped at the Output Pins
A full adder computes the arithmetic sum of three 1-bit inputs (A, B, and Cin), producing a 1-bit Sum and a 1-bit carry-out (Cout).
Expected behavior:
| A | B | Cin | Sum | Cout | |-----|-----|-------|-------|--------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |
Simulation shows Sum = 0 and Cout = 1 for inputs A=1, B=0, Cin=0. The outputs do not match the expected arithmetic result. Inspect the circuit and correct the fault.
Constraints
- Do not change the internal logic gates.
- Ensure the final output matches standard full adder behavior.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.