Decoder with Enable Logic
Memory mapped systems and peripheral buses require address decoding to select specific devices. A standard decoder always drives one output high, which can cause bus contention or unintended writes if the device should not be active. To prevent this, system decoders incorporate a chip select or enable signal that safely forces all outputs low when the device is idle.
This module decodes a 3-bit binary input into an 8-bit output vector. It includes an active-high enable signal. When the enable signal is asserted, exactly one bit of the output corresponding to the binary value of the input is driven high. When the enable signal is deasserted, all output bits are forced to zero regardless of the input value.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | en | input | 1 | Active-high enable signal; output is 8'b00000000 when low | | sel | input | 3 | Binary selection input | | out | output | 8 | Decoded output; one-hot when en is 1, all zeros when en is 0 |
Constraints
- The circuit is purely combinational; no clock or reset signals are used.
- The output must be exactly 8'b00000000 when
enis 0, overriding any value onsel. - The output must be strictly one-hot when
enis 1.
Topics
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