Parameterized Equality Comparator
Reusable IP blocks require parameterization to adapt to different data paths without duplicating code. A fundamental building block in any digital library is a width-agnostic equality comparator used in match filters, cache tags, and branch condition evaluators.
The module compares two input vectors of identical, parameterized width. It asserts a single-bit output high if all corresponding bits in the two input vectors are identical. The output is driven low if any bit position differs.
This is a purely combinational circuit. There is no clock or reset. The output must reflect the comparison of the current inputs at all times.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | WIDTH| parameter | integer| Bit-width of the inputs; defaults to 8 | | a | input | WIDTH| First operand | | b | input | WIDTH| Second operand | | eq | output | 1 | Asserts to 1 if a and b are strictly equal; 0 otherwise |
Constraints
- The module must correctly handle any positive integer value for
WIDTH, including 1. - The output
eqmust be exactly 1 bit wide regardless of the input width. - The design must be purely combinational with no latches or registers.
- The default value for the
WIDTHparameter must be 8.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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