Instruction Decoder using Casez
Microprocessors decode fetched instructions to determine the required datapath operations. This decoding step must quickly identify the instruction type by examining specific opcode bits while completely ignoring payload bits like register addresses, offsets, or immediate values. Standard Verilog case statements require explicit enumeration of every possible bit pattern, which is highly inefficient for variable-length opcodes.
The module evaluates a 16-bit instruction word and classifies it into one of eight categories using a 3-bit output instr_type. It also asserts an is_valid signal for recognized instructions. The instruction set uses variable-length opcodes. The number of bits that define the instruction type changes depending on the instruction class.
The instruction set architecture defines the following decode rules, where ? represents a bit that can be either 0 or 1:
- NOP:
16'b0000_0000_0000_0000setsinstr_typeto3'b000andis_validto1 - ADD:
16'b0001_????_????_????setsinstr_typeto3'b001andis_validto1 - SUB:
16'b0010_????_????_????setsinstr_typeto3'b010andis_validto1 - LOAD:
16'b0100_????_????_????setsinstr_typeto3'b011andis_validto1 - STORE:
16'b0101_????_????_????setsinstr_typeto3'b100andis_validto1 - JMP:
16'b10??_????_????_????setsinstr_typeto3'b101andis_validto1 - BEQ:
16'b110?_????_????_????setsinstr_typeto3'b110andis_validto1 - INVALID: Any other bit pattern sets
instr_typeto3'b111andis_validto0
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | instr | input | 16 | The 16-bit instruction word to be decoded | | instr_type | output | 3 | The decoded instruction category | | is_valid | output | 1 | Asserted to 1 if the instruction matches a recognized pattern, 0 otherwise |
Constraints
- The design must be purely combinational with no clocks, latches, or reset logic.
- All 65,536 possible input combinations must resolve to deterministic outputs.
- Unrecognized instructions must explicitly set
is_validto0andinstr_typeto3'b111.
Topics
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