Digital Combination Lock
Secure access panels and electronic safes rely on finite state machines to validate user entry sequences. The digital combination lock processes sequential button presses and asserts an unlock signal only when the exact programmed sequence is entered.
The correct sequence to unlock the system is b1 followed by b0 followed by b1. State transitions occur on the rising edge of clk.
A valid button press is registered when exactly one of b0 or b1 is high. If neither button is pressed (b0 = 0 and b1 = 0), the system must hold its current state. If an incorrect button for the sequence is pressed, or if both buttons are pressed simultaneously, the system must immediately return to the idle state. The unlock output must be 1 only when the lock has successfully reached the final unlocked state. The rst signal is asynchronous and active-high.
| Current State | b1 | b0 | Next State | unlock | |---------------|------|------|------------|----------| | Idle | 0 | 0 | Idle | 0 | | Idle | 1 | 0 | S1 | 0 | | Idle | 0 | 1 | Idle | 0 | | Idle | 1 | 1 | Idle | 0 | | S1 | 0 | 0 | S1 | 0 | | S1 | 0 | 1 | S2 | 0 | | S1 | 1 | 0 | Idle | 0 | | S1 | 1 | 1 | Idle | 0 | | S2 | 0 | 0 | S2 | 0 | | S2 | 1 | 0 | S3 | 0 | | S2 | 0 | 1 | Idle | 0 | | S2 | 1 | 1 | Idle | 0 | | S3 | 0 | 0 | S3 | 1 | | S3 | 1 | 0 | Idle | 1 | | S3 | 0 | 1 | Idle | 1 | | S3 | 1 | 1 | Idle | 1 |
Constraints
- Implement a Moore finite state machine using D-type flip-flops.
- Route the asynchronous
rstsignal to the reset pin of all state elements. - Any invalid input sequence must strictly route the next-state logic to the idle state.
Topics
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