Glitchless Clock Multiplexer
Dynamic clock scaling in modern SoCs requires switching between asynchronous frequency domains on the fly. A naive multiplexer produces runt pulses or glitches during the transition, causing instant system crashes.
The glitchless clock multiplexer safely routes one of two free-running, asynchronous clocks to a single output. When sel changes, the circuit must wait for the currently active clock to go low before disabling it. It then waits for the newly selected clock to go low before enabling it. This guarantees that clk_out never experiences a shortened high or low pulse.
Steady-state behavior:
| sel | clk_0 | clk_1 | clk_out | |-------|---------|---------|-----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 1 | 1 |
Constraints
- Use negative edge-triggered D flip-flops for all synchronization logic.
- Implement cross-coupled feedback to prevent both clock enables from being active simultaneously.
- Gate the final clock outputs using AND gates before combining them with an OR gate.
Topics
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