Asynchronous Reset Synchronizer
Large digital systems require resets that assert immediately to handle dead-clock conditions but deassert cleanly with the clock edge to prevent recovery time violations. The asynchronous reset synchronizer bridges this gap by asserting the internal reset asynchronously and releasing it synchronously.
The circuit takes an active-low asynchronous reset rst_ni and a clock clk. It outputs a synchronized active-low reset rst_no. When rst_ni goes low, rst_no must immediately go low regardless of the clock state. When rst_ni goes high, rst_no must transition high only after two consecutive rising edges of clk.
| Sequence | rst_ni | clk | rst_no | |----------|----------|-------|----------| | Assert | 0 | 0 | 0 | | Deassert | 1 | 0 | 0 | | Edge 1 | 1 | 1 | 0 | | Hold | 1 | 0 | 0 | | Edge 2 | 1 | 1 | 1 |
Constraints
- Implement using exactly two D flip-flops with asynchronous active-low reset pins.
- Tie the data input of the first flip-flop to logic high (1).
- Connect the external asynchronous reset directly to the reset pins of both flip-flops.
Topics
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