The Latch vs Flip Flop Timing Trap
High-performance processor designs frequently use level-sensitive latches instead of edge-triggered flip-flops to squeeze out extra picoseconds of performance through time borrowing.
The circuit diagram shows a synchronous data path starting at flip-flop FF1, passing through a negative-level transparent latch L1, and ending at flip-flop FF2. All sequential elements share a common clock. The clock period is T_clk = 1000 ps with a 50% duty cycle, starting with a rising edge at 0 ps.
The combinational logic delay before the latch is T_comb1 = 600 ps. The combinational logic delay after the latch is T_comb2. The setup time for all sequential elements is T_setup = 50 ps. The clock-to-Q delay for the flip-flops is T_cq = 100 ps. The D-to-Q propagation delay for the transparent latch is T_dq = 80 ps.
Calculate the exact arrival times across this pipeline and determine the maximum allowable delay for T_comb2 without violating setup constraints at FF2.
Constraints
- Clock edges are ideal with zero skew and zero jitter.
- The delay values provided represent the maximum (worst-case) delays.
- Hold time checks are ignored for this analysis.
- Time borrowing is permitted as long as setup constraints are met before the latch closes.
Topics
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