Overlapping Sequence Detector with Timeout
Network packet parsers and serial protocol monitors must recover gracefully from dropped connections. Implementing timeout mechanisms directly within a state machine causes state explosion, requiring a decoupled counter architecture.
Construct a sequence detector that identifies the overlapping pattern 1011 on the din input. The state machine must advance only when valid is 1. If valid remains 0 for 15 consecutive clock cycles, the sequence detector must reset to its initial state regardless of previous progress. Assert match to 1 for one cycle immediately when the sequence is completely detected.
Constraints
- Use a separate 4-bit counter for the timeout logic.
- Do not implement the timeout as 15 distinct states in the main sequence FSM.
- Reset the 4-bit counter to 0 synchronously whenever
validis 1. - Force the sequence FSM to its initial state when the counter reaches 15.
Topics
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