Off By One Cycle in State Machine Timeout
Hardware interfaces use timeout counters to abort stalled bus transactions and return to a safe idle state. A timeout circuit asserts the timeout signal high for exactly one clock cycle after the en signal has been held high for 4 consecutive clock cycles.
Expected behavior:
When rst is 1, the internal counter resets and timeout is 0. When en is 1, the counter increments each active clock edge. On the 4th consecutive cycle of en being 1, timeout must evaluate to 1. If en drops to 0, or immediately after timeout asserts, the internal counter resets to 0.
Simulation shows timeout is 0 on the 4th cycle of en being high. The timeout signal instead asserts on the 5th cycle. The timeout evaluation is delayed by one clock cycle.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the state registers or add new flip-flops.
- You may only change the combinatorial logic evaluating the terminal count.
- The circuit must resolve the timeout in exactly 4 cycles, not 5.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.