Self-Correcting Ring Counter: One-Hot Detection Circuit
High-speed state machines and token-passing arbiters often rely on ring counters for glitch-free control. Because electrical noise can flip a bit and derail the sequence permanently, robust designs include self-correcting logic to detect invalid states and force a recovery.
Design the next-state logic for a 4-bit self-correcting ring counter. The circuit must evaluate the current state inputs Q3, Q2, Q1, and Q0. A valid state is strictly one-hot. If the state is valid, the circuit performs a standard right shift. If the state is invalid (zero-hot or multi-hot), it asserts an internal invalid condition and forces the next state outputs D3, D2, D1, and D0 to 1000.
| Q3 | Q2 | Q1 | Q0 | D3 | D2 | D1 | D0 | |------|------|------|------|------|------|------|------| | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Constraints
- Combinational logic only.
- Determine one-hot validity by combining an XOR parity check with a combinational check that rejects any state with multiple HIGH bits.
- Do not use behavioral adders or equality operators to check the state.
Topics
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