Divide by Five with Fifty Percent Duty Cycle

HardVerilog / SystemVerilogBuild

High-speed communication interfaces often require derived clocks with precise 50% duty cycles to ensure balanced setup and hold times across the system. When dividing a clock by an even number, achieving a 50% duty cycle is trivial. However, dividing by an odd number like five requires utilizing both edges of the source clock to create half-cycle resolutions.

The module receives a high-frequency input clock clk_in and generates an output clock clk_out whose frequency is exactly one-fifth of the input. To maintain a perfect 50% duty cycle, clk_out must remain high for exactly 2.5 input clock cycles and low for exactly 2.5 input clock cycles.

To achieve this, the design must utilize a mod-5 counter operating on the positive edge of the input clock to generate an intermediate signal. A delayed version of this signal must then be sampled on the negative edge. Finally, these two signals are logically combined to produce the final 50% duty cycle output.

| Signal | Direction | Width | Description | |-----------|-----------|-------|-------------| | clk_in | input | 1 | High-frequency input clock | | rst_n | input | 1 | Asynchronous active-low reset; clk_out goes to 0 when asserted | | clk_out | output | 1 | Divide-by-5 output clock with 50% duty cycle |

Timing and Reset Rules

Clock edges: The design requires sequential logic triggered on both the posedge and negedge of clk_in.
Reset type: rst_n is an asynchronous active-low reset.
Reset behavior: When rst_n is 0, all internal counters, intermediate flip-flops, and clk_out must immediately go to 0.
Output logic: The final clk_out is a combinational combination of the positive-edge and negative-edge triggered registers.

Worked Trace

This trace details the state of the internal positive-edge counter, the output, and the half-cycle progression.

Cycle 1 (posedge): rst_n=0, clk_in=1 → count=0, clk_out=0
Cycle 1 (negedge): rst_n=1, clk_in=0 → clk_out=0
Cycle 2 (posedge): clk_in=1 → count=0, clk_out=1
Cycle 2 (negedge): clk_in=0 → clk_out=1
Cycle 3 (posedge): clk_in=1 → count=1, clk_out=1
Cycle 3 (negedge): clk_in=0 → clk_out=1
Cycle 4 (posedge): clk_in=1 → count=2, clk_out=1
Cycle 4 (negedge): clk_in=0 → clk_out=0
Cycle 5 (posedge): clk_in=1 → count=3, clk_out=0
Cycle 5 (negedge): clk_in=0 → clk_out=0
Cycle 6 (posedge): clk_in=1 → count=4, clk_out=0
Cycle 6 (negedge): clk_in=0 → clk_out=0
Cycle 7 (posedge): clk_in=1 → count=0, clk_out=1 (wrap)

Timing Diagram

{ "signal": [
  { "name": "clk_in",  "wave": "01010101010101010101" },
  { "name": "rst_n",   "wave": "00111111111111111111" },
  { "name": "count",   "wave": "2.2.2.2.2.2.2.2.2.2.", "data": ["0", "0", "0", "1", "2", "3", "4", "0", "1", "2"] },
  { "name": "t1",      "wave": "00011110000011110000" },
  { "name": "t2",      "wave": "00001111000001111000" },
  { "name": "clk_out", "wave": "00011111000001111100" }
], "head": { "text": "Divide by 5 with 50% duty cycle using positive and negative edge mixing." } }

Constraints

The reset rst_n must be asynchronous and active-low.
clk_out must strictly follow a 50% duty cycle; it must be high for exactly 2.5 cycles and low for exactly 2.5 cycles.
On reset, clk_out must evaluate to 0 immediately.

Topics

Clock Domain CrossingSequential LogicCounters

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