Divide by Four Using Counter
Digital systems frequently require slower, synchronized clocks for low-power peripherals or slower processing domains. A power-of-two clock divider safely generates these frequencies using a simple binary counter.
The module takes a high-speed input clock and outputs a clock running at exactly one-quarter the frequency. By incrementing a 2-bit counter on every clock cycle, the most significant bit naturally toggles at one-quarter the rate of the input clock. Extracting the divided clock directly from this register bit provides a clean, glitch-free clock signal for downstream logic.
The circuit uses a positive-edge triggered clock and an asynchronous active-low reset. On reset, the internal counter and the output clock must both be forced to 0.
Cycle 1: rst_n=0 → count=0, clk_out=0 Cycle 2: rst_n=1 → count=1, clk_out=0 Cycle 3: rst_n=1 → count=2, clk_out=1 Cycle 4: rst_n=1 → count=3, clk_out=1 Cycle 5: rst_n=1 → count=0, clk_out=0 Cycle 6: rst_n=1 → count=1, clk_out=0
{ "signal": [
{ "name": "clk_in", "wave": "p........." },
{ "name": "rst_n", "wave": "01........" },
{ "name": "count", "wave": "=...=...=.", "data": ["0","1","2","3","0","1","2","3","0"] },
{ "name": "clk_out", "wave": "0...1...0." }
], "head": { "text": "The most significant bit of the 2-bit counter provides the divided clock." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_in | input | 1 | Positive-edge triggered input clock | | rst_n | input | 1 | Asynchronous active-low reset; forces clk_out to 0 | | clk_out | output | 1 | Divided clock running at one-quarter the frequency of clk_in |
Constraints
- The module must trigger on the positive edge of
clk_in - The reset must be asynchronous and active-low
- The output clock
clk_outmust be identically zero whenrst_nis asserted - The output clock must be derived directly from the most significant bit of an internal 2-bit counter to prevent glitches
Topics
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