Divide by Three with Fifty Percent Duty Cycle

High-speed serial interfaces and DDR memory controllers often require exactly symmetrical clocks at odd division ratios to meet tight setup and hold time requirements. A standard counter-based divider produces an asymmetric duty cycle for odd divisors, which can cause severe timing violations in double-data-rate applications.

The module divides the input clock clk_in by three while maintaining a perfect 50% duty cycle. The output clock clk_out must remain high for exactly 1.5 cycles of clk_in and low for exactly 1.5 cycles. This requires leveraging both the positive and negative edges of the source clock to achieve the half-cycle shift.

• Clock edge: Both posedge and negedge of clk_in must be used to generate the correct output phase.
• Reset type: Asynchronous.
• Reset polarity: Active-low (rst_n).
• Output values on reset: All internal states and the output clk_out must evaluate to 0 when rst_n is 0.

Cycle 1 (posedge): rst_n=0, clk_in=0 → clk_out=0 Cycle 2 (posedge): rst_n=1, clk_in=1 → internal counter increments, clk_out transitions to 1 Cycle 2 (negedge): rst_n=1, clk_in=0 → clk_out remains 1 Cycle 3 (posedge): rst_n=1, clk_in=1 → clk_out remains 1 Cycle 3 (negedge): rst_n=1, clk_in=0 → clk_out transitions to 0 (exactly 1.5 cycles after rising) Cycle 4 (posedge): rst_n=1, clk_in=1 → clk_out remains 0 Cycle 4 (negedge): rst_n=1, clk_in=0 → clk_out remains 0 Cycle 5 (posedge): rst_n=1, clk_in=1 → clk_out transitions to 1 (exactly 1.5 cycles after falling)

{ "signal": [
  { "name": "clk_in",  "wave": "0101010101010101" },
  { "name": "rst_n",   "wave": "0011111111111111" },
  { "name": "clk_out", "wave": "0001110001110001" }
], "head": { "text": "Divide by 3 with 50% duty cycle" } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk_in | input | 1 | Source clock | | rst_n | input | 1 | Asynchronous active-low reset; clk_out goes to 0 when asserted | | clk_out | output | 1 | Divided clock with 50% duty cycle; resets to 0 |

Constraints

• Output clk_out must have exactly a 50% duty cycle.
• Reset is asynchronous and active-low.
• clk_out must be exactly 0 while rst_n is 0.
• The design must use both posedge clk_in and negedge clk_in to achieve the half-cycle resolution.
• clk_out must not glitch high immediately when reset is released; the first high pulse must begin strictly on the first positive clock edge after reset deassertion.

Topics

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