Dual Asynchronous Reset and Set

High-reliability systems often require flip-flops that can be forced to a known safe state (reset) or a specific active state (set) independently of the clock signal. When both signals are asserted simultaneously, the hardware synthesis tool must infer a priority structure to prevent metastability or undefined behavior.

The circuit is a D-type flip-flop with an active-low asynchronous reset and an active-low asynchronous set. The output follows the data input on the rising edge of the clock under normal operation. If the reset signal is asserted, the output immediately goes low regardless of the clock or set signal. If the set signal is asserted while the reset signal is inactive, the output immediately goes high regardless of the clock.

• Clock edge: posedge clk
• Reset: Asynchronous, active-low (rst_n)
• Set: Asynchronous, active-low (set_n)
• Reset priority: rst_n has strict priority over set_n when both are asserted simultaneously.
• Output q is registered and resets to 0 when rst_n is 0, or goes to 1 when set_n is 0 (and rst_n is 1).

Cycle 1: rst_n=0, set_n=0, d=1 → q=0 (Reset has priority over set) Cycle 2: rst_n=1, set_n=0, d=1 → q=1 (Set is asserted asynchronously) Cycle 3: rst_n=1, set_n=1, d=0 → q=0 (Normal operation, latches d=0) Cycle 4: rst_n=1, set_n=0, d=1 → q=1 (Set is asserted asynchronously) Cycle 5: rst_n=1, set_n=1, d=1 → q=1 (Normal operation, latches d=1) Cycle 6: rst_n=1, set_n=1, d=0 → q=0 (Normal operation, latches d=0) Cycle 7: rst_n=0, set_n=1, d=1 → q=0 (Reset is asserted asynchronously) Cycle 8: rst_n=0, set_n=0, d=1 → q=0 (Reset has priority over set)

{
  "signal": [
    { "name": "clk",   "wave": "p......." },
    { "name": "rst_n", "wave": "01.....0" },
    { "name": "set_n", "wave": "0.101..0" },
    { "name": "d",     "wave": "1.01.01." },
    {},
    { "name": "q",     "wave": "0101.0.." }
  ],
  "head": { "text": "Asynchronous reset overrides set; normal operation resumes when both are high." }
}

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; forces output to 0 | | set_n| input | 1 | Asynchronous active-low set; forces output to 1 when rst_n is 1 | | d | input | 1 | Data input | | q | output | 1 | Registered data output |

Constraints

• Clock edge is positive, reset and set are active-low.
• Output q evaluates to 0 on reset, 1 on set.
• Priority rule: rst_n takes strict precedence over set_n when both are asserted simultaneously (i.e., both are 0).
• Both reset and set must evaluate asynchronously to the clock.
• Output q is registered and must hold its value when both reset and set are deasserted and no clock edge occurs.
• All signals are 1-bit wide.

Topics

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