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Codiode/Problems/Combinational Logic

Equality versus Case Equality

HardLogic CircuitAnalyze

Verification testbenches rely on precise comparisons to identify uninitialized states or high-impedance drivers.

The scenario presents two 4-bit vectors, A and B, compared using both the standard logical equality operator (==) and the case equality operator (===). Vector A is driven with the value 4'b10x1. Vector B is driven with the exact same value 4'b10x1. The results of these comparisons drive two single-bit outputs: Y_logical captures the result of A == B, and Y_case captures the result of A === B.

Determine the exact bit values evaluated at Y_logical and Y_case. Analyze how each operator handles unknown bits during simulation and synthesis.

Constraints

  • Standard equality evaluates to an unknown state if any bit in either operand is unknown or high-impedance.
  • Case equality treats unknown and high-impedance states as literal values to match perfectly.
  • Synthesizable RTL must only rely on standard logical operators.

Topics

verilogsimulationoperatorsx-states

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