Unknown X Literals Propagation
Uninitialized registers and floating inputs in Verilog simulations manifest as unknown X values that can easily mask critical reset bugs.
The schematic shows a combinational logic block with three inputs A, B, and C, and one output Y. Input A is driven by an uninitialized flip-flop, forcing its simulation value to 1'bx. Input B is tied to 1'b1 and input C is tied to 1'b0. The logic evaluates the expression Y = (A & B) | (A & C).
Determine the propagated value at output Y and analyze how the unknown literal interacts with standard logic gates.
Constraints
- Input
Astrictly evaluates to the four-state logic value1'bx. - Bitwise operations in Verilog follow standard IEEE 1364 four-state logic truth tables.
- The circuit contains no sequential elements or delays.
Topics
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