Fix a Static-1 Hazard
Asynchronous control paths and unclocked reset pins require glitch-free signals to prevent false triggers. A static-1 hazard causes a momentary dip to 0 during input transitions between adjacent prime implicants.
Implement a hazard-free version of the logic function Y = (A AND B) OR ((NOT A) AND C). The circuit must maintain a steady logic 1 when B and C are both 1, regardless of the transition of A.
| A | B | C | Y | |-----|-----|-----|-----| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 |
Constraints
- Implement the sum-of-products form using exactly three AND gates, one NOT gate, and one OR gate.
- Combinational logic only.
- Do not use multiplexers or XOR gates.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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