Trace the Glitch Through a Circuit: Which Gate Path Causes the Static-1 Hazard
Physical logic gates have non-zero propagation delays that can cause temporary false outputs during state transitions. The circuit implements the Boolean expression Y = AB + A'C using a standard sum-of-products architecture. Signal A feeds directly into the first AND gate and passes through an inverter to reach the second AND gate. Inputs B and C are held at logic 1. Trace the internal node values when input A transitions from 1 to 0. Determine the timing of the intermediate signals and identify the resulting glitch at the output Y.
Constraints
- Assume all basic logic gates (AND, OR, NOT) have an equal, non-zero propagation delay of
t_pd. - Wire delays are negligible and can be ignored.
- Inputs
BandCare stable at logic 1 well before and during the transition ofA.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.