Identify a Static-1 Hazard from a K-Map
Glitches in combinational logic can trigger false clock edges or asynchronous resets in downstream sequential circuits. The provided logic implements the Boolean function Y = A'B + AC + A'C' using a two-level sum-of-products architecture. The Karnaugh map for this function contains exactly three prime implicants covering all the 1-cells.
Analyze the K-map to locate adjacent 1-cells that are not enclosed within the same prime implicant. Identify the specific input transition that exposes a static-1 hazard and determine the conditions under which the output Y momentarily drops to 0.
Constraints
- Assume all logic gates have a non-zero, finite propagation delay.
- The NOT gate on input
Aintroduces a delay beforeA'evaluates. - The circuit uses standard AND, OR, and NOT gates without redundant logic.
Topics
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