Fixed Point Format Alignment
Digital signal processors cannot directly add values with different radix points. Hardware must physically align the implicit fractional boundaries of fixed-point numbers before routing them to an arithmetic logic unit.
The circuit receives two 4-bit unsigned inputs: A in Q2.2 format and B in Q3.1 format. Align both inputs into a common 5-bit Q3.2 format. Add the aligned values and output the 5-bit sum Y.
Format definitions: * A (Q2.2): 2 integer bits, 2 fractional bits. * B (Q3.1): 3 integer bits, 1 fractional bit. * Y (Q3.2): 3 integer bits, 2 fractional bits.
Constraints
- Combinational logic only.
- Treat all input and output signals as unsigned values.
- Ignore any carry-out bit from the 5-bit addition.
Topics
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