FSM Enum to Integer Casting

Hardware controllers often sequence through states that correspond directly to configuration memory addresses. By defining the finite state machine (FSM) states as a strongly typed enumeration with explicit integer values, the state variable can be directly cast and used as a memory index, avoiding redundant address generation logic.

The module implements a 5-state sequence controller. The FSM advances through S_IDLE (0), S_CMD1 (1), S_CMD2 (2), S_DATA (3), and S_DONE (4) when the advance input is asserted, wrapping back to S_IDLE. The current state must be cast to a 3-bit integer to drive the state_idx output. This integer also serves as the direct address to a hardcoded lookup table (LUT) to drive the lut_data output.

The LUT contents are fixed as follows: • Index 0 (S_IDLE): 8'hA1 • Index 1 (S_CMD1): 8'hB2 • Index 2 (S_CMD2): 8'hC3 • Index 3 (S_DATA): 8'hD4 • Index 4 (S_DONE): 8'hE5 • Indices 5 to 7: 8'h00

The FSM operates on the positive edge of clk. The rst_n signal is an asynchronous, active-low reset that forces the FSM into the S_IDLE state. Both state_idx and lut_data are combinational outputs that immediately reflect the current state of the FSM.

Cycle 1: rst_n=0, advance=X → state_idx=0, lut_data=8'hA1 (S_IDLE) Cycle 2: rst_n=1, advance=1 → state_idx=1, lut_data=8'hB2 (S_CMD1) Cycle 3: rst_n=1, advance=0 → state_idx=1, lut_data=8'hB2 (hold) Cycle 4: rst_n=1, advance=1 → state_idx=2, lut_data=8'hC3 (S_CMD2) Cycle 5: rst_n=1, advance=1 → state_idx=3, lut_data=8'hD4 (S_DATA) Cycle 6: rst_n=1, advance=1 → state_idx=4, lut_data=8'hE5 (S_DONE)

flowchart LR
    RESET(( )) -->|reset| S_IDLE
    S_IDLE((S_IDLE)) -->|advance=1| S_CMD1
    S_IDLE -->|advance=0| S_IDLE
    S_CMD1((S_CMD1)) -->|advance=1| S_CMD2
    S_CMD1 -->|advance=0| S_CMD1
    S_CMD2((S_CMD2)) -->|advance=1| S_DATA
    S_CMD2 -->|advance=0| S_CMD2
    S_DATA((S_DATA)) -->|advance=1| S_DONE
    S_DATA -->|advance=0| S_DATA
    S_DONE((S_DONE)) -->|advance=1| S_IDLE
    S_DONE -->|advance=0| S_DONE

{ "signal": [
  { "name": "clk",       "wave": "p......" },
  { "name": "rst_n",     "wave": "01....." },
  { "name": "advance",   "wave": "x10111." },
  {},
  { "name": "state_idx", "wave": "======.", "data": ["0", "1", "1", "2", "3", "4"] },
  { "name": "lut_data",  "wave": "======.", "data": ["8'hA1", "8'hB2", "8'hB2", "8'hC3", "8'hD4", "8'hE5"] }
], "head": { "text": "FSM sequence showing state casting and LUT addressing" } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; resets FSM to S_IDLE | | advance | input | 1 | When 1, advances FSM to the next state on posedge clk | | state_idx | output | 3 | Combinational output of the current state cast to a 3-bit integer | | lut_data | output | 8 | Combinational LUT output addressed by state_idx |

Constraints

• The clock edge must be posedge clk and the reset must be an active-low asynchronous rst_n.
• Upon reset, state_idx must output 3'b000 and lut_data must output 8'hA1.
• The lut_data output must be exactly 8 bits wide.
• Unused LUT indices (5, 6, and 7) must output 8'h00 if addressed.
• The state machine must wrap directly from S_DONE (4) back to S_IDLE (0) when advance is asserted.

Topics

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