Full Subtractor from Half Subtractors
Arithmetic Logic Units (ALUs) rely on hierarchical modularity to scale up complex operations. Multi-bit subtractors cascade single-bit stages to compute differences and propagate borrows across wide data paths.
The circuit must compute A minus B minus Bin. It must produce a difference bit D and a borrow-out bit Bout.
| A | B | Bin | D | Bout | |-----|-----|-------|-----|--------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 |
Constraints
- Build the circuit using exactly two Half Subtractor blocks and exactly one OR gate.
- Do not use discrete XOR, AND, or NOT gates to compute the core logic.
- Implement strictly as a combinational circuit with no sequential elements.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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