Identifying Implicit State
Unintended combinational loops in digital design create accidental latches that break synthesis tools and ruin static timing analysis.
The schematic displays a logic block built entirely from combinational gates with inputs A, B, and C, and a single output Y. The circuit consists of two AND gates and one OR gate. The output of the first AND gate is driven by A and B. This output feeds into the first input of the OR gate. The second input to the OR gate comes from the second AND gate, which is driven by input C and a feedback connection from the main output Y.
Trace the signal paths and evaluate the steady-state behavior of Y under all input conditions. Identify the specific input combinations that cause the circuit to exhibit sequential behavior.
Constraints
- Assume ideal gates with zero propagation delay for logical analysis.
- All inputs transition cleanly without glitches.
- The circuit powers up in an unknown state.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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