Serial Parity Generator
Serial communication protocols require continuous error checking without storing the entire payload in memory. A serial parity generator calculates the parity bit on the fly during transmission and makes it available immediately after the data packet concludes.
Calculate the running even parity of a serial data stream. The circuit must maintain a state that updates on every clock cycle where valid is 1. When valid is 1, the next state incorporates data_in into the running parity using an XOR operation. When valid is 0, the state holds its current value. When rst is 1, the state resets to 0 synchronously. The output parity_out continuously reflects the current state.
| rst | valid | data_in | parity_out | next_state | |-------|---------|-----------|--------------|--------------| | 1 | 1 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 1 | | 0 | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 |
Constraints
- Use exactly one D flip-flop component for state storage.
- Implement the synchronous reset using combinational logic before the flip-flop input.
- Do not gate the clock signal.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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