IEEE 754 Normalization Shifter
Floating point adders and multipliers often produce unnormalized results that must be corrected before write-back. The normalization stage restores the hidden one format by shifting the mantissa left and decrementing the exponent by the exact shift amount.
The circuit receives an 8-bit unnormalized mantissa M_in, a 4-bit exponent E_in, and a 3-bit leading zero count LZC.
Produce an 8-bit normalized mantissa M_out by logically shifting M_in left by LZC bits. Zero-fill the lower bits during the shift. Produce a 4-bit adjusted exponent E_out by subtracting LZC from E_in.
Constraints
- Combinational logic only.
- Do not use sequential elements or clock signals.
- Assume
E_inis always strictly greater than or equal toLZCto prevent underflow.
Topics
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