If Else Priority Encoder
Microcontrollers receive multiple hardware interrupt requests simultaneously and must decide which to service first. An interrupt controller resolves these simultaneous requests by assigning a strict priority hierarchy to each source. When synthesized, cascaded conditional statements naturally form a priority routing structure in hardware.
The module evaluates an 8-bit interrupt request vector and outputs the index of the highest-priority active interrupt. Interrupt 0 (the least significant bit) has the highest priority, and interrupt 7 (the most significant bit) has the lowest priority. If any interrupt is active, a valid flag is asserted.
This module is purely combinational. There is no clock or reset.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | irq | input | 8 | Interrupt request vector; each bit represents an independent interrupt source | | irq_id | output | 3 | Index of the highest priority active interrupt; defaults to 0 if none are active | | valid | output | 1 | Asserted (1) if at least one interrupt is active, 0 otherwise |
Constraints
- The circuit must be purely combinational with no latches
irq[0]possesses the highest priority, whileirq[7]possesses the lowest priority- When
irqis all zeros,irq_idmust explicitly output 0 andvalidmust output 0
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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