Implement a Full Adder Sum and Carry Using Two 4:1 MUXes
Arithmetic logic units often synthesize complex Boolean functions using multiplexers to optimize for specific FPGA architectures or standard cell libraries. A full adder can be decomposed into two independent routing functions driven by shared select lines.
Implement the sum and carry-out logic of a full adder.
| A | B | Cin | Sum | Cout | |-----|-----|-------|-------|--------| | 0 | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | 1 | | 1 | 1 | 0 | 0 | 1 | | 1 | 1 | 1 | 1 | 1 |
Constraints
- Use exactly two 4:1 multiplexers.
- Connect
AandBto the select lines of both multiplexers. - Drive the multiplexer data inputs using only
Cin, an invertedCin, or constant logic values. - Use at most one NOT gate.
- Do not use any AND, OR, NAND, NOR, or XOR gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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