Implicit Net Type Fallacy
A full adder computes the single-bit sum and carry of two 1-bit inputs plus a carry-in. Full adders are the atomic unit of every ripple-carry and carry-lookahead adder chain. In a hierarchical multi-bit adder, a typo in any one internal wire name creates a silent disconnection that corrupts all higher-order bit positions without producing a compile error under default Verilog net type rules.
The solution module accepts A, B, and Cin and drives Sum and Cout. All logic is purely combinational and gate-level.
Simulation shows Cout = 0 for inputs A = 1, B = 1, Cin = 0 and A = 0, B = 1, Cin = 1. The carry output fails to assert when expected. The module compiles without errors, but silent logic disconnections exist. Inspect the code and correct the fault.
| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | A | input | 1 | First operand | | B | input | 1 | Second operand | | Cin | input | 1 | Carry input | | Sum | output | 1 | XOR sum of A, B and Cin | | Cout | output | 1 | Carry output; asserted when two or more inputs are 1 |
Constraints
- All logic is purely combinational; no clock or flip-flops.
- Do not alter the module interface or port definitions.
- You must add `
- All internal wires must be explicitly declared.
Topics
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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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