Basic Gate Instantiation
Netlist patching and precise timing control sometimes require hardware engineers to bypass synthesis inference and instantiate exact logic gates manually. Structural Verilog allows designers to explicitly define the physical gates and their interconnections, which is critical when implementing specific standard cell architectures or applying late-stage engineering change orders.
A half adder computes the sum and carry of two single-bit binary inputs. The computation relies strictly on basic logic gates. The sum output represents the logical exclusive-OR of the two inputs. The carry output represents the logical AND of the two inputs.
For this module, the logic must be implemented using built-in structural primitives rather than behavioral operators or continuous assignments.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a | input | 1 | First single-bit operand | | b | input | 1 | Second single-bit operand | | sum | output | 1 | Least significant bit of the addition | | carry| output | 1 | Carry-out bit of the addition |
Constraints
- The design must use explicit Verilog gate primitives like
and,or,xor, ornot - Behavioral continuous assignments using logical operators are not permitted
- Procedural blocks are not permitted
- The module is purely combinational; there is no clock or reset
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.