Named Port Connection
Complex arithmetic logic units often have many configuration flags, data inputs, and status outputs. When integrating third-party hardware IP or updating existing modules, relying on positional port connections is a major source of bugs because any change to the sub-module's port order will silently break the integration. Named port connections explicitly map the parent signals to the child ports, making the design robust against port list modifications.
The solution module acts as a wrapper that instantiates a pre-existing module named alu_core. The alu_core module is already defined in the compilation environment. The parent wrapper module must connect its own inputs and outputs to the alu_core instance using explicit named port connections.
This circuit is purely combinational. There are no clocks or resets involved.
Parent Wrapper Ports (`solution`)
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | a_in | input | 8 | First operand for the ALU | | b_in | input | 8 | Second operand for the ALU | | op_sel | input | 3 | Operation selector | | c_in | input | 1 | Carry input | | alu_out | output | 8 | Result from the ALU | | c_out | output | 1 | Carry output | | z_flag | output | 1 | Zero flag output | | ovf_flag | output | 1 | Overflow flag output |
Sub-Module Ports (`alu_core`)
You must instantiate alu_core and map the wrapper ports to these exact sub-module port names:
| Sub-Module Port | Direction | Width | Map to Wrapper Signal | |-----------------|-----------|-------|-----------------------| | operand_a | input | 8 | a_in | | operand_b | input | 8 | b_in | | opcode | input | 3 | op_sel | | carry_in | input | 1 | c_in | | result | output | 8 | alu_out | | carry_out | output | 1 | c_out | | zero_flag | output | 1 | z_flag | | overflow_flag | output | 1 | ovf_flag |
Constraints
- You must instantiate the
alu_coremodule inside yoursolutionmodule. - You must use explicit named port connections for every signal.
- Do not implement the logic for
alu_coreyourself; assume it is already defined and available to the linker. - The circuit is purely combinational; do not use any edge-triggered logic.
Topics
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