Swapped Named Connections
Large system-on-chip designs require instantiating sub-modules with hundreds of ports. Relying on positional port connections in these environments becomes unmaintainable and highly error-prone. Named connections solve this by explicitly linking parent signals to child ports, making the instantiation completely order-independent.
A pre-defined module named logic_core is provided in the environment. It performs bitwise AND and OR operations on two 4-bit inputs. The module defines four ports: a_in, b_in, c_out, and d_out. The top-level module solution receives two 4-bit inputs and must drive two 4-bit outputs. The logic_core module must be instantiated and connected using named port mapping. To prove that named connections are order-independent, the instantiation must list the child module's ports in strictly reverse alphabetical order.
The connections between the top module and the sub-module must be mapped as follows: • logic_core port a_in connects to top-level in_1 • logic_core port b_in connects to top-level in_2 • logic_core port c_out connects to top-level out_and • logic_core port d_out connects to top-level out_or
| Signal | Direction | Width | Description | |-----------|-----------|-------|-------------| | in_1 | input | 4 | First 4-bit operand | | in_2 | input | 4 | Second 4-bit operand | | out_and | output | 4 | Bitwise AND result from the sub-module | | out_or | output | 4 | Bitwise OR result from the sub-module |
Constraints
- The design is strictly combinational; there is no clock or reset
- You must instantiate the provided
logic_coremodule - You must use named connections for the instantiation
- The named connections must be listed in strictly reverse alphabetical order of the child module's ports:
.d_out,.c_out,.b_in,.a_in
Topics
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