Implicit Shift Register via Concatenation
Serial communication interfaces like SPI and I2C rely heavily on shift registers to convert bitstreams into parallel data words. While shift registers can be built using explicit bit-by-bit assignments or loops, hardware engineers typically use the concatenation operator to express the shift operation concisely and cleanly.
This module operates as an 8-bit left-shifting register. On every active clock edge, the current 8-bit value shifts left by one position. The new serial input is shifted into the least significant bit (LSB), and the previous most significant bit (MSB) is discarded. The entire 8-bit register state is continuously driven to the output.
The design is driven by a positive-edge triggered clock. It features an active-low asynchronous reset that clears the register to zero immediately when asserted.
Cycle 1: rst_n=0, d_in=0 → q_out=8'b00000000 (Asynchronous reset) Cycle 2: rst_n=1, d_in=1 → q_out=8'b00000000 (Input 1 applied) Cycle 3: rst_n=1, d_in=0 → q_out=8'b00000001 (Input 1 shifted in, Input 0 applied) Cycle 4: rst_n=1, d_in=1 → q_out=8'b00000010 (Input 0 shifted in, Input 1 applied) Cycle 5: rst_n=1, d_in=1 → q_out=8'b00000101 (Input 1 shifted in) Cycle 6: rst_n=1, d_in=0 → q_out=8'b00001011 (Input 1 shifted in)
{ "signal": [
{ "name": "clk", "wave": "p....." },
{ "name": "rst_n", "wave": "01...." },
{ "name": "d_in", "wave": "010110" },
{},
{ "name": "q_out", "wave": "======", "data": ["00", "00", "01", "02", "05", "0B"] }
], "head": { "text": "Shift register operation showing bit accumulation over time." } }| Signal | Direction | Width | Description | |---------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears q_out to 8'b00000000 | | d_in | input | 1 | Serial data input, shifted into the LSB | | q_out | output | 8 | 8-bit parallel output of the shift register |
Constraints
- Clock is positive-edge triggered
- Reset is asynchronous and active-low
- Output
q_outmust be registered - Output resets to 8'b00000000
- The shift direction must be left towards the MSB
Topics
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