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Codiode/Problems/Sequential Logic

Logic Type Continuous vs Procedural

EasyVerilog / SystemVerilogBuild

SystemVerilog introduced the logic data type to unify the traditional wire and reg types found in Verilog. A common point of confusion for engineers transitioning to SystemVerilog is whether logic can be driven by continuous assignments or if it is restricted to procedural blocks. This module proves that a single data type seamlessly handles both contexts.

The module computes two identical 8-bit 2-to-1 multiplexers. Both multiplexers receive the same data inputs and selection signal. The first multiplexer output must be driven using a continuous assignment statement. The second multiplexer output must be driven using a procedural combinational block.

This circuit is entirely combinational. There is no clock or reset. The outputs must update immediately whenever any input changes. When the selection signal is 0, the outputs reflect the first data input. When the selection signal is 1, the outputs reflect the second data input.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in0 | input | 8 | First data input; selected when sel is 0 | | in1 | input | 8 | Second data input; selected when sel is 1 | | sel | input | 1 | Selection control signal | | out_cont | output | 8 | Multiplexer output driven by an assign statement | | out_proc | output | 8 | Multiplexer output driven by an always_comb block |

Constraints

  • The module must be named solution.
  • All ports must be declared using the logic data type.
  • The out_cont signal must be driven by an assign statement.
  • The out_proc signal must be driven by an always_comb block.
  • The circuit is purely combinational; outputs must not be registered.

Topics

CombinationalMultiplexerData TypesSystemVerilog

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Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.

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