Memory Initialization via Reset Block

Embedded systems and secure enclaves often require memory arrays to be explicitly cleared to a known state upon reset to prevent data leakage from previous power cycles or soft resets. When file reading commands are unavailable or unsynthesizable, resetting a memory block requires sequential logic to iterate through all addresses and overwrite them.

The solution module is a 16-word by 8-bit single-port synchronous RAM with an automatic initialization sequence. Upon reset, the module suspends normal memory operations and sequentially writes zero to every memory address. Once all 16 addresses are cleared, it asserts a ready flag and acts as a standard synchronous RAM, allowing normal reads and writes.

Timing and Reset Rules: • Clock edge: posedge clk • Reset type: Synchronous, active-high rst • During reset and initialization (ready is 0): data_out outputs 8'h00 and any external writes (we is 1) are ignored. • Initialization sequence: When rst is 1, ready becomes 0 on the next clock cycle and the internal initialization address resets to 0. When rst goes low, the module writes 8'h00 to the current internal address and increments the address each cycle. After writing to address 15, ready becomes 1 on the next clock cycle. • During normal operation (ready is 1): The module acts as a standard read first synchronous RAM. On the positive clock edge, if we is 1, data_in is written to addr; regardless of we, data_out updates to the previous value stored at addr. • If rst is asserted at any time, the initialization process immediately restarts.

Worked Trace: Cycle 1: rst=1 → (On posedge) ready=0, internal counter=0 Cycle 2: rst=0 → (On posedge) mem[0]=0, internal counter=1 Cycle 3: rst=0 → (On posedge) mem[1]=0, internal counter=2 ... Cycle 17: rst=0 → (On posedge) mem[15]=0, ready=1 Cycle 18: rst=0, we=1, addr=5, data_in=8'hAA → (On posedge) mem[5]=8'hAA, data_out=0 Cycle 19: rst=0, we=0, addr=5 → (On posedge) data_out=8'hAA

{ "signal": [
  { "name": "clk",      "wave": "p................." },
  { "name": "rst",      "wave": "010..............0" },
  { "name": "ready",    "wave": "10...............1" },
  { "name": "we",       "wave": "0................." },
  { "name": "addr",     "wave": "x................." },
  { "name": "data_in",  "wave": "x................." },
  { "name": "data_out", "wave": "=0...............=", "data": ["D", "0"] }
], "head": { "text": "Initialization phase taking 16 cycles after reset drops." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst | input | 1 | Synchronous active-high reset | | we | input | 1 | Write enable for normal operation | | addr | input | 4 | Memory address for read and write operations | | data_in | input | 8 | Data to be written to memory | | data_out | output | 8 | Data read from memory; outputs 0 during initialization | | ready | output | 1 | Status flag; 1 when initialization is complete |

Constraints

• The memory must be exactly 16 words deep and 8 bits wide.
• rst is synchronous and active-high.
• External reads and writes must be completely ignored while ready is 0.
• data_out must be strictly 8'h00 while ready is 0.
• data_out updates synchronously on posedge clk.
• The memory must exhibit read first behavior during normal writes.

Topics

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