Metastability Injection for Simulation

Standard RTL simulation does not model metastability. When a signal crosses clock domains without proper synchronization, standard flip-flop models will simply latch the old or new value flawlessly, hiding critical Clock Domain Crossing (CDC) bugs that will inevitably fail in silicon. To catch these bugs during simulation, verification engineers use behavioral flip-flop models that actively monitor timing and inject unknown states (1'bx) when timing is violated, forcing downstream logic to prove it can handle the metastability.

The meta_ff module models a D flip-flop with configurable SETUP_TIME and HOLD_TIME parameters. It tracks the simulation time of d transitions and clk positive edges. If the d input changes too close to the clock edge, the output q is driven to 1'bx to simulate a metastable state.

• clk is a positive-edge triggered clock.
• rst_n is an asynchronous, active-low reset. When asserted, q immediately becomes 0 and any pending timing violations are cleared.
• A setup violation occurs if d transitions strictly less than SETUP_TIME before a posedge clk. Upon a setup violation, q becomes 1'bx at the clock edge.
• A hold violation occurs if d transitions strictly less than HOLD_TIME after a posedge clk. Upon a hold violation, q becomes 1'bx immediately when the d transition occurs.
• If no violation occurs, q takes the value of d at the posedge clk.
• You may assume d will never transition at the exact same simulation time step as the clock edge.

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; clears output to 0 | | d | input | 1 | Data input | | q | output | 1 | Registered data output; becomes 1'bx on timing violation |

Constraints

• The module must be named solution.
• The module must declare two parameters: SETUP_TIME (default 2) and HOLD_TIME (default 2).
• Timing checks must use strictly less than (<). A transition exactly at the setup or hold time boundary is safe and does not cause a violation.
• Hold violations must corrupt the output to 1'bx immediately upon the illegal d transition, not at the next clock edge.
• Reset is asynchronous and must immediately override any 1'bx state.

Topics

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