MISR Signature Aliasing
Built-In Self-Test (BIST) engines compress thousands of output responses into a compact signature to verify circuit health. The circuit below represents a 2-bit Multiple Input Signature Register (MISR) fed by a logic block under test. The inputs are IN0 and IN1. The register state is held in two flip-flops, Q0 and Q1, which are initialized to 0 at startup.
The next-state logic is defined by the Boolean expressions Q0_next = IN0 ^ Q1 and Q1_next = IN1 ^ Q0, where ^ denotes the logical XOR operation.
Determine the final state signatures for specific input sequences and identify error patterns that result in signature aliasing.
Constraints
- The MISR is initialized to
Q0 = 0andQ1 = 0before Cycle 0. ^represents the logical XOR operation.- State updates happen simultaneously at the end of each clock cycle.
- An error sequence
Erepresents the XOR difference between the faulty input and the fault-free input.
Topics
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