Mixed Edge Flip Flops
High-speed interfaces and specific clocking architectures often require data to be launched on one edge of a clock and captured on the opposite edge. While this technique halves the available time for combinational logic to propagate between the registers, it is essential for double data rate (DDR) interfaces and precise phase alignments.
This module implements a half-cycle timing path. It samples an 8-bit input d_in on the rising edge of the clock into an intermediate register. The output of this intermediate register is bitwise inverted. The inverted value is then sampled on the falling edge of the clock into the final output register q_out.
The clock signal is clk. The reset signal is rst_n, which is asynchronous and active-low. On reset, both the intermediate rising-edge register and the final falling-edge register must be cleared to 0.
Worked Trace: Cycle 1: rst_n=0 • q_rise=8'h00, q_out=8'h00 Cycle 2 (posedge): rst_n=1, d_in=8'hAA • q_rise=8'hAA Cycle 2 (negedge): rst_n=1 • q_out=8'h55 Cycle 3 (posedge): rst_n=1, d_in=8'hAA • q_rise=8'hAA Cycle 3 (negedge): rst_n=1 • q_out=8'h55 Cycle 4 (posedge): rst_n=1, d_in=8'hF0 • q_rise=8'hF0 Cycle 4 (negedge): rst_n=1 • q_out=8'h0F Cycle 5 (posedge): rst_n=1, d_in=8'hF0 • q_rise=8'hF0 Cycle 5 (negedge): rst_n=1 • q_out=8'h0F Cycle 6 (posedge): rst_n=1, d_in=8'h33 • q_rise=8'h33 Cycle 6 (negedge): rst_n=1 • q_out=8'hCC Cycle 7 (posedge): rst_n=1, d_in=8'h33 • q_rise=8'h33 Cycle 7 (negedge): rst_n=1 • q_out=8'hCC Cycle 8 (posedge): rst_n=1, d_in=8'h33 • q_rise=8'h33 Cycle 8 (negedge): rst_n=1 • q_out=8'hCC
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "d_in", "wave": "x=..=..=", "data": ["AA", "F0", "33"] },
{ "name": "q_rise", "wave": "==..=..=", "data": ["00", "AA", "F0", "33"] },
{ "name": "q_out", "wave": "==..=..=", "data": ["00", "55", "0F", "CC"] }
], "head": { "text": "Intermediate register updates on posedge, output register updates on negedge." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Clock signal; triggers intermediate register on posedge and output register on negedge | | rst_n | input | 1 | Asynchronous active-low reset; all registers go to 0 when asserted | | d_in | input | 8 | Data input | | q_out | output | 8 | Inverted data output, updated on the negative clock edge |
Constraints
- Output
q_outmust update on the negative edge ofclk. - The intermediate register must update on the positive edge of
clk. - Both registers must be asynchronously reset to 8'h00 when
rst_nis 0. - The combinational logic between the registers must perform a bitwise NOT operation.
Topics
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