Multiplier Accumulation Array
High-performance arithmetic logic units rely on dense adder arrays to compute multiplication results in a single clock cycle. The accumulation array reduces a matrix of partial products down to a final sum by aligning and adding bits of equal binary weight.
The circuit must sum three 3-bit partial product vectors into a 6-bit final product. The input vectors represent the pre-computed bitwise AND combinations of a 3x3 multiplier. Because each vector corresponds to a different multiplier bit, they must be shifted according to their positional weight before summation.
The output prod must equal the sum: pp0 + (pp1 << 1) + (pp2 << 2).
| pp2 | pp1 | pp0 | prod | |-------|-------|-------|--------| | 0 | 0 | 0 | 0 | | 0 | 0 | 7 | 7 | | 0 | 7 | 0 | 14 | | 7 | 0 | 0 | 28 | | 7 | 7 | 7 | 49 |
Constraints
- Use only primitive Full Adder and Half Adder components.
- Do not use multi-bit addition blocks.
- Implement using strictly combinational logic.
Topics
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