Out of Bounds Enum Default State
High-reliability systems operating in aerospace or high-radiation environments are susceptible to Single Event Upsets (SEUs). A cosmic ray or power fluctuation can flip a register bit, forcing a state machine into an unmapped encoding. If the RTL does not explicitly handle these phantom states, the system can lock up indefinitely.
The module solution implements a 3-state control sequence: IDLE (2'b00), ACTIVE (2'b01), and DONE (2'b10). To test radiation resilience, the module includes a synchronous injection interface that forces the internal state register to an arbitrary value. If the state machine finds itself in the undefined state (2'b11), it must immediately recover by transitioning back to IDLE on the next clock cycle. Normal transitions proceed from IDLE to ACTIVE when go is 1, ACTIVE to DONE when finish is 1, and DONE to IDLE when ack is 1.
Positive-edge triggered clk and asynchronous active-low rst_n govern the timing. The output state_out resets to 2'b00. The inject_en signal is synchronous and takes priority over normal state transitions, forcing state_out to take the value of inject_state on the next clock edge.
Cycle 1: rst_n=0 → state_out=00 (IDLE) Cycle 2: rst_n=1, go=1 → state_out=01 (ACTIVE) Cycle 3: go=0, inject_en=1, inject_state=3 → state_out=11 (ILLEGAL) Cycle 4: inject_en=0 → state_out=00 (IDLE auto-recovery) Cycle 5: go=1 → state_out=01 (ACTIVE) Cycle 6: finish=1 → state_out=10 (DONE)
flowchart LR
RESET(( )) -->|reset| IDLE
IDLE((IDLE)) -->|go=1| ACTIVE
IDLE -->|go=0| IDLE
ACTIVE((ACTIVE)) -->|finish=1| DONE
ACTIVE -->|finish=0| ACTIVE
DONE((DONE)) -->|ack=1| IDLE
DONE -->|ack=0| DONE
ILLEGAL(["2'b11 ★"]):::out -.->|auto-recover| IDLE
classDef out fill:#6C5CE7,stroke:#5B4FE8,color:#fff{ "signal": [
{ "name": "clk", "wave": "p......" },
{ "name": "rst_n", "wave": "01....." },
{ "name": "go", "wave": "010.10." },
{ "name": "finish", "wave": "0.....1" },
{ "name": "inject_en", "wave": "0.10..." },
{ "name": "inject_state", "wave": "x.3x...", "data": ["3"] },
{},
{ "name": "state_out", "wave": "=======", "data": ["0", "0", "1", "3", "0", "1", "2"] }
], "head": { "text": "State machine recovering from an injected illegal state." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; forces state_out to 2'b00 | | go | input | 1 | Transitions state from IDLE to ACTIVE | | finish | input | 1 | Transitions state from ACTIVE to DONE | | ack | input | 1 | Transitions state from DONE to IDLE | | inject_en | input | 1 | Synchronous enable that forces state_out to inject_state | | inject_state | input | 2 | The state value to inject when inject_en is 1 | | state_out | output | 2 | Current FSM state; resets to 2'b00 |
Constraints
- Positive-edge triggered clock and asynchronous active-low reset.
- Output
state_outmust be registered and reset to 2'b00. - The
inject_ensignal takes priority over all normal state transitions. - If the state register contains 2'b11, it must unconditionally transition to 2'b00 on the next clock edge.
- If multiple transition inputs are asserted simultaneously, the FSM only evaluates the input relevant to its current state.
Topics
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