Parameterized Delay Line
Hardware pipelines frequently require control signals or data to be delayed by a precise number of clock cycles to synchronize with parallel processing paths. Manually writing out dozens of flip-flop instantiations is rigid, verbose, and error-prone.
A parameterized delay line shifts an input signal through a chain of registers. The input d_in propagates through DEPTH flip-flops before emerging at d_out. You must use a generate for loop to create this cascaded structure, chaining the output of stage i to the input of stage i+1.
The circuit operates on the positive edge of clk. An asynchronous, active-low reset rst_n clears all flip-flops in the chain to 0 immediately when asserted.
- Cycle 1:
rst_n=0,d_in=0→ Clock edge samples reset. All FFs = 0,d_out=0 - Cycle 2:
rst_n=1,d_in=1→ Clock edge samplesd_in=1. FF1=1, others=0.d_out=0 - Cycle 3:
rst_n=1,d_in=0→ Clock edge samplesd_in=0. FF2=1.d_out=0 - Cycle 4:
rst_n=1,d_in=1→ Clock edge samplesd_in=1. FF3=1, FF1=1.d_out=0 - Cycle 5:
rst_n=1,d_in=0→ Clock edge samplesd_in=0. FF4=1, FF2=1.d_out=1 - Cycle 6:
rst_n=1,d_in=0→ Clock edge samplesd_in=0. FF3=1.d_out=0 - Cycle 7:
rst_n=1,d_in=0→ Clock edge samplesd_in=0. FF4=1.d_out=1 - Cycle 8:
rst_n=1,d_in=0→ Clock edge samplesd_in=0. All FFs=0.d_out=0
{ "signal": [
{ "name": "clk", "wave": "p......." },
{ "name": "rst_n", "wave": "01......" },
{ "name": "d_in", "wave": "01010000" },
{},
{ "name": "d_out", "wave": "0...1010" }
], "head": { "text": "Cycle-by-cycle propagation for DEPTH=4." } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | DEPTH| parameter | - | Integer default 4. Number of delay stages. | | clk | input | 1 | Positive-edge triggered clock | | rst_n| input | 1 | Asynchronous active-low reset; clears all stages to 0 | | d_in | input | 1 | Data input | | d_out| output | 1 | Data output, delayed by DEPTH clock cycles |
Constraints
- You must use a
generateloop to instantiate the register stages. - The reset must be asynchronous and active-low.
- All flip-flops in the chain must reset to
0. - The module must correctly parameterize the number of stages using
DEPTH.
Topics
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