Positional Port Connection
Hardware designs rely heavily on modularity, where complex systems are built by instantiating smaller, verified sub-blocks. When connecting a sub-module into a higher-level design, Verilog allows ports to be mapped by their declared position rather than by name. This approach is concise but requires the designer to know the exact port order of the underlying module.
The top-level wrapper module receives standard control and data signals and passes them to a pre-defined sub-module named hidden_dff. The sub-module acts as a standard D-type flip-flop. The instantiation must map the top-level ports to the sub-module strictly by their positional order.
The flip-flop is driven by a positive-edge triggered clock clk. It uses an asynchronous, active-low reset rst_n. When rst_n is 0, the output q is forced to 0 immediately, regardless of the clock state. On the positive edge of clk, if rst_n is 1, q takes the value of d.
Cycle 1: rst_n=0, d=0 → q=0 Cycle 2: rst_n=1, d=1 → q=1 Cycle 3: rst_n=1, d=0 → q=0 Cycle 4: rst_n=0, d=1 → q=0
{ "signal": [
{ "name": "clk", "wave": "p..." },
{ "name": "rst_n", "wave": "01.0" },
{ "name": "d", "wave": "0101" },
{},
{ "name": "q", "wave": "0100" }
], "head": { "text": "Flip-flop operation with asynchronous reset" } }| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; q goes to 0 when asserted | | d | input | 1 | Data input | | q | output | 1 | Registered data output |
Constraints
- You must instantiate the
hidden_dffmodule inside yoursolutionmodule. - You must connect the ports of
hidden_dffusing strictly positional mapping. - The clock edge is positive and the reset is asynchronous active-low.
- The output
qmust reset to 0.
Topics
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