Priority Case Encoder Inference

Hardware systems with multiple peripherals rely on interrupt controllers to manage service requests efficiently. When multiple devices assert their interrupt lines simultaneously, the controller must enforce a strict priority scheme to ensure critical events are handled first. Using explicit priority logic ensures that synthesis tools correctly infer the designer's intent without generating unnecessary hardware.

The module receives an 8-bit interrupt request vector where bit 0 represents the highest priority device and bit 7 represents the lowest. On every clock cycle, it evaluates the request vector. If any requests are active, it asserts a valid flag and outputs the 3-bit identifier of the winning interrupt. The lowest active index always wins. If no requests are active, the valid flag is de-asserted and the identifier is set to 0.

• Positive-edge triggered clock (clk).
• Asynchronous active-low reset (rst_n).
• On reset, valid is 0 and irq_id is 0.
• All outputs are registered and updated on the positive edge of clk.
• If multiple bits in req are asserted simultaneously, the lowest index takes priority.

Cycle 1: rst_n=0, req=8'bxxxx_xxxx → valid=0, irq_id=0 (Reset) Cycle 2: rst_n=1, req=8'b0000_0000 → valid=0, irq_id=0 (No active request) Cycle 3: rst_n=1, req=8'b0000_0001 → valid=1, irq_id=0 (Highest priority device 0) Cycle 4: rst_n=1, req=8'b1000_0000 → valid=1, irq_id=7 (Lowest priority device 7) Cycle 5: rst_n=1, req=8'b1000_0001 → valid=1, irq_id=0 (Simultaneous requests, device 0 wins) Cycle 6: rst_n=1, req=8'b0010_0100 → valid=1, irq_id=2 (Simultaneous requests, device 2 wins) Cycle 7: rst_n=1, req=8'b0000_0000 → valid=0, irq_id=0 (Requests cleared)

{ "signal": [
  { "name": "clk",    "wave": "p......." },
  { "name": "rst_n",  "wave": "01......" },
  { "name": "req",    "wave": "x======.", "data": ["8'h00", "8'h01", "8'h80", "8'h81", "8'h24", "8'h00"] },
  {},
  { "name": "valid",  "wave": "0.1...0." },
  { "name": "irq_id", "wave": "=..====.", "data": ["0", "7", "0", "2", "0"] }
], "head": { "text": "Cycle-by-cycle behavior of the priority interrupt encoder." } }

| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | clk | input | 1 | Positive-edge triggered clock | | rst_n | input | 1 | Asynchronous active-low reset; all outputs go to 0 when asserted | | req | input | 8 | Interrupt request vector; bit 0 is highest priority | | valid | output | 1 | Asserted high when at least one request is active; registered | | irq_id | output | 3 | Index of the highest priority active request; registered |

Constraints

• Clock is positive-edge triggered.
• Reset is asynchronous and active-low.
• On reset, valid must be 0 and irq_id must be 0.
• irq_id must be exactly 3 bits.
• All outputs must be registered.
• If multiple bits in req are asserted, the lowest index takes priority.
• When req is 0, valid must be 0 and irq_id must be 0.

Topics

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