Reduction AND NAND
Determining if all bits in a wide bus are asserted is a frequent requirement in digital design. Hardware systems use this logic to detect a terminal count in a timer, verify a fully populated bitmask, or confirm that all parallel subsystems have asserted their ready signals. Manually coding massive logical AND chains is brittle and unmaintainable when bus widths change.
This module evaluates a parameterised input bus and asserts a flag when every bit in the bus is high. It also produces a complementary flag that is asserted when any bit in the bus is low. Both outputs must dynamically scale with the parameterised width without requiring code modifications.
This is a purely combinational circuit. Changes on the input must immediately reflect on the outputs without requiring a clock or reset.
Parameters
| Parameter | Default | Description | |-----------|---------|-------------| | WIDTH | 8 | The bit width of the input bus |
Ports
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | in | input | WIDTH | Parameterised input bus | | all_ones | output | 1 | Asserted high when all bits of in are 1 | | not_all_ones | output | 1 | Asserted high when at least one bit of in is 0 |
Constraints
- The design must be purely combinational with no latches or flip-flops
- The design must support any
WIDTHgreater than 1 - Do not use procedural loops to iterate through the bits
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
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