Reduction XOR Parity Generator
Serial communication protocols rely on parity bits to detect single bit errors during data transmission. A transmitter calculates a parity bit based on the payload and appends it to the message before sending it over the wire.
The module receives an 8-bit data payload and computes a single even parity bit. For even parity, the total number of set bits across the payload and the parity bit combined must be an even number. The parity output is asserted high if the input payload contains an odd number of ones, and driven low if the input payload contains an even number of ones.
This is a purely combinational circuit. There is no clock or reset signal. The output must reflect the input continuously.
| Signal | Direction | Width | Description | |--------|-----------|-------|-------------| | data_in | input | 8 | The 8-bit data payload | | parity_out | output | 1 | Even parity bit; 1 if data_in has an odd number of ones, 0 otherwise |
Constraints
- The circuit must be purely combinational.
- Do not use clocks, resets, or sequential logic.
- The output must be exactly 1 bit wide.
- The parity calculation must treat zero ones as an even number.
Topics
Solve this problem
Write the module in Verilog, SystemVerilog or VHDL. Your submission is compiled and simulated against a real testbench — you get the waveform back, not a stored answer.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.